Name
Title | ||
|---|---|---|
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. |
Abstract | ||
|---|---|---|
To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect ... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ASYNC.2009.11 | ASYNC |
Keywords | Field | DocType |
m-out-of-n encoded circuits,casual observer,fine-grain leakage power reduction,incorrect operation,multi-threshold-voltage transistors,informal analysis,quasi delay-insensitive logic,asynchronous,transistors,power dissipation,crosstalk,sleep,voltage,logic gates,protocols,energy dissipation,combinational circuits,benchmark testing,threshold voltage,low power electronics | Logic gate,Idle,Voltage,Electronic engineering,Power gating,Engineering,Electronic circuit,Transistor,Electrical engineering,Threshold voltage,Low-power electronics | Conference |
ISSN | Citations | PageRank |
1522-8681 | 5 | 0.63 |
References | Authors | |
13 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masashi Imai | 1 | 26 | 3.38 |
| Kouei Takada | 2 | 5 | 0.63 |
| Takashi Nanya | 3 | 200 | 35.46 |