Name
Abstract | ||
|---|---|---|
A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-µm technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/TVLSI.2004.830919 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
design mapping technology,communication architecture,on-chip integration,sustained on-chip communication,new scalable single-chip communication,prototype asoc device,design process,design reuse,compile-time scheduled communication,scalable on-chip communication,asoc communication,system on a chip,adaptive signal processing,computer architecture,process design,adaptive systems,system on chip,vlsi,chip,clock rate,integrated circuit design,application software,adaptive system,hardware | System on a chip,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,Process design,Encoder,Application software,Very-large-scale integration,Clock rate,Scalability,Embedded system | Journal |
Volume | Issue | ISSN |
12 | 7 | 1063-8210 |
Citations | PageRank | References |
47 | 2.70 | 22 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jian Liang | 1 | 47 | 2.70 |
| Andrew Laffely | 2 | 64 | 5.66 |
| Sriram Srinivasan | 3 | 379 | 27.92 |
| Russell Tessier | 4 | 888 | 93.99 |