Name
Title | ||
|---|---|---|
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture |
Abstract | ||
|---|---|---|
Elliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4-${\rm mm}^{2}$ 160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 $\mu{\rm J}$ for one ${\rm GF}(p)/{\rm GF}(2^{m})$ ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TVLSI.2013.2237930 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
efficient power-analysis-resistant dual-field elliptic curve cryptographic processor,power-analysis attacks,heterogeneous dual-processing-element architecture,portable application,private key,heterogeneous processing-element architecture,parallel computations,elliptic curve cryptography (ecc),right-to-left double-and-add-always ec scalar multiplication,dual fields,microprocessor chips,df-ecc chip,private key cryptography,dual-pe design,cmos digital integrated circuits,hardware efficiency,side-channel information leakage,randomized processing technique,memory hierarchy,ecc functions,dedicated hardware architecture,local memory synchronization scheme,computational complexity,wireless channels,crypto-ic,priority-oriented scheduling,public key cryptography,size 90 nm,power-analysis-resistant df-ecc processor,information exchange security,cmos technology,heterogeneous dual-pe architecture,data bandwidth,synchronisation | Power analysis,Scalar multiplication,Memory hierarchy,Information leakage,Computer science,Electronic engineering,Real-time computing,Bandwidth (signal processing),Elliptic curve cryptography,Public-key cryptography,Embedded system,Hardware architecture | Journal |
Volume | Issue | ISSN |
22 | 1 | 1063-8210 |
Citations | PageRank | References |
16 | 0.65 | 21 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jen-Wei Lee | 1 | 78 | 5.59 |
| Szu-Chi Chung | 2 | 38 | 2.91 |
| Hsie-Chia Chang | 3 | 474 | 49.13 |
| Chen-Yi Lee | 4 | 1211 | 152.40 |