Name
Abstract | ||
|---|---|---|
process technologies advance to the subwavelength era, the 1-D design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. To improve the printability of 1-D cell design, it is essential to insert dummy patterns and optimize line-end gap distribution for each layer. This paper presents novel 1-D cell generation algorithms that simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, minimize used routing tracks, insert sufficient dummy patterns, and eliminate stage-like line-end gaps without power and timing overhead. Consequently, the 1-D cell area is minimized and the printability of the cell is enhanced. To the best of our knowledge, this is also the first work in the literature that considers line-end gap distribution during 1-D cell generation. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCAD.2012.2226454 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
transistor placement and routing,1d cell generation,1d design style,lithography-aware cell generation,gridded design rule,cell generation,line-end gap distribution optimization,lithography,integrated circuit design,printability enhancement | Journal | 32 |
Issue | ISSN | Citations |
3 | 0278-0070 | 5 |
PageRank | References | Authors |
0.47 | 11 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Po-Hsun Wu | 1 | 52 | 6.05 |
| Mark Po-Hung Lin | 2 | 165 | 16.87 |
| Tung-Chieh Chen | 3 | 486 | 27.19 |
| Tsung-Yi Ho | 4 | 1061 | 95.20 |
| Yu-Chuan Chen | 5 | 8 | 1.23 |
| Shun-Ren Siao | 6 | 5 | 0.47 |
| Shu-Hung Lin | 7 | 7 | 0.84 |