Name
Abstract | ||
|---|---|---|
Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic C... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1049/iet-cds:20080070 | IET Circuits, Devices & Systems |
Keywords | Field | DocType |
CMOS logic circuits,logic gates | Logic gate,Leakage (electronics),Dissipation,16-bit,CMOS,Electronic engineering,Robustness (computer science),OR gate,Dynamic logic (digital electronics),Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
2 | 6 | 1751-858X |
Citations | PageRank | References |
9 | 0.62 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Frustaci | 1 | 25 | 2.44 |
| P. Corsonello | 2 | 50 | 5.31 |
| S. Perri | 3 | 44 | 3.23 |
| G. Cocorullo | 4 | 11 | 1.71 |