Title
A Memory-Efficient Hardware Architecture For A Pulse Doppler Radar Vehicle Detector
Abstract
In this paper, we propose a memory-efficient structure for a pulse Doppler radar in order to reduce the hardware's complexity. The conventional pulse Doppler radar is computed by fast frequency transform (FFT) of all range cells in order to extract the velocity of targets. We observed that this method requires a huge amount of memory to perform the FFT processes for all of the range cells. Therefore, instead of detecting the velocity of all range cells, the proposed architecture extracts the velocity of the targets by using the cells related to the moving targets. According to our simulations and experiments, the detection performance of this proposed architecture is 93.5%, and the proposed structure can reduce the hardware's complexity by up to 66.2% compared with the conventional structure.
Year
DOI
Venue
2011
10.1587/transfun.E94.A.1210
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
Keywords
Field
DocType
pulse Doppler radar, FFT, memory-efficient hardware, Doppler shift
Pulse-Doppler radar,Continuous-wave radar,Radar engineering details,Computer vision,Theoretical computer science,Fast Fourier transform,Artificial intelligence,Doppler effect,Computer hardware,Detector,Mathematics,Hardware architecture
Journal
Volume
Issue
ISSN
E94A
5
0916-8508
Citations 
PageRank 
References 
1
0.39
0
Authors
2
Name
Order
Citations
PageRank
Sang Dong Kim1359.22
Jonghun Lee26714.55