Name
Abstract | ||
|---|---|---|
Combined with dynamic voltage and frequency scaling (DVFS), power gating can be used effectively to improve the overall power efficiency of a chip design. Since the DVFS is applied to multiple supply voltage levels, the design tradeoffs between supply noise and power saving can vary significantly across different operating points. Hence, the tradeoffs have to be considered carefully by designers. In this paper, a systematic design tradeoff analysis for power gating geared towards DVFS applications is presented. We propose a multi-driver based scheme to drive sleep transistors. Re-routable decoupling capacitance based design strategies are used to balance supply noises and power saving at different supply levels. Finally, we demonstrate a simulation-based automatic design flow to improve the performance of power delivery network. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISQED.2012.6187523 | ISQED |
Keywords | Field | DocType |
supply levels,power aware computing,driver circuits,dynamic voltage and frequency scaling,power-gating,transistor circuits,power saving,power efficiency,power gating,re-routable decoupling capacitance based design strategy,leakage saving,systematic design tradeoff analysis,power supply circuits,supply noises,multidriver based scheme,integrated circuit noise,integrated circuit design,supply voltage levels,dvfs,power delivery network,dvfs applications,design tradeoffs,drive sleep transistors,chip design,supply noise,simulation-based automatic design flow,transistors,leakage current,chip,switches,noise,design flow,logic gates | Electrical efficiency,Capacitance,Computer science,Voltage,Design flow,Electronic engineering,Real-time computing,Power gating,Integrated circuit design,Frequency scaling,Transistor | Conference |
ISSN | ISBN | Citations |
1948-3287 | 978-1-4673-1034-5 | 1 |
PageRank | References | Authors |
0.35 | 5 | 2 |