Name
Abstract | ||
|---|---|---|
We propose new multistage interconnection networks (MIN) for scalable parallel Viterbi decoder architectures. The architecture consists of the desired number of processing elements (PE) connected by the suggested MINs, thus allowing a tradeoff between complexity and speed. The structure of the MIN is derived first by transforming the de Bruijn interconnection-based Viterbi algorithm trellis into t... |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/TCOMM.2003.816998 | IEEE Transactions on Communications |
Keywords | Field | DocType |
Multiprocessor interconnection networks,Viterbi algorithm,Shift registers,Maximum likelihood decoding,Convolutional codes,Maximum likelihood estimation,State estimation,Markov processes,Communications Society,Australia | Shift register,Computer science,Parallel computing,Multistage interconnection networks,Shuffling,Viterbi decoder,Encoder,De Bruijn sequence,Interconnection,Viterbi algorithm | Journal |
Volume | Issue | ISSN |
51 | 9 | 0090-6778 |
Citations | PageRank | References |
7 | 0.67 | 13 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Akopian | 1 | 84 | 12.44 |
| J. Takala | 2 | 37 | 4.80 |
| Jukka Saarinen | 3 | 264 | 46.21 |
| J. Astola | 4 | 1174 | 138.74 |