Name
Abstract | ||
|---|---|---|
As a major sequential logic element, D flip-flop is an indispensible cell in logic cell library. In this paper, we proposed two improved sub-threshold D flip-flop circuits (mTGMS and emC 2MOS D flip-flop) after conducting robustness analysis of several typical flip-flop circuits. Using SMIC 0.18um CMOS technology, the simulation results show that the minimum work voltage of our proposed mTGMS and emC 2MOS is 0.19V and 0.18V, the minimum average power is 13.2pW and 14.1pW, while the minimum Power Delay Product (PDP) is 13aJ and 4.35aJ respectively. © 2011 IEEE. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/VLSISoC.2011.6081623 | VLSI-SOC |
Keywords | Field | DocType |
d flip-flop,sub-threshold circuit,ultra-low power,robustness,multiplexing,wireless sensor networks,logic gates,sequential circuits | Logic gate,Power–delay product,Sequential logic,Robustness (computer science),Electronic engineering,CMOS,Engineering,Flip-flop,Electronic circuit,Wireless sensor network | Conference |
Volume | Issue | Citations |
null | null | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Jin | 1 | 83 | 25.25 |
| Sheng Lu | 2 | 8 | 2.49 |
| Weifeng He | 3 | 9 | 2.65 |
| Zhigang Mao | 4 | 199 | 41.73 |