Name
Title | ||
|---|---|---|
High effective-resolution built-in jitter characterization with quantization noise shaping |
Abstract | ||
|---|---|---|
A novel built-in jitter characterization architecture combining quantization noise shaping and a partial Vernier delay structure is proposed for high resolution jitter measurement. The effective resolution is optimized at the system level as well as the circuit level. Using 90nm CMOS technology, an area of 0.008mm2 is occupied. The power consumption is 1.85mW. An effective resolution of 1.5ps is achieved. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2024724.2024896 | DAC |
Keywords | Field | DocType |
cmos integrated circuits,partial vernier delay structure,power consumption,high effective-resolution built-in jitter,built-in jitter characterization,high resolution jitter measurement,jitter,system level,circuit level,high-resolution jitter measurement,delays,cmos technology,quantization noise shaping,noise shaping,integrated circuit noise,novel built-in jitter characterization,size 90 nm,gated ring oscillator,power 1.85 mw,quantization noise,vernier delay line,effective resolution,quantization,ring oscillator,noise,high resolution | Computer science,Vernier scale,Electronic engineering,CMOS,Noise shaping,Jitter,Quantization (signal processing),Electrical engineering,System level,Power consumption | Conference |
ISSN | ISBN | Citations |
0738-100x | 978-1-4503-0636-2 | 0 |
PageRank | References | Authors |
0.34 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Leyi Yin | 1 | 14 | 1.76 |
| Yong-tae Kim | 2 | 206 | 31.51 |
| Peng Li | 3 | 1912 | 152.85 |