Name
Title | ||
|---|---|---|
Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach (Research Note) |
Abstract | ||
|---|---|---|
The technology and application trends leading to current day multiprocessor architectures such as chip multiprocessors, embedded architectures, and massively parallel architectures, demand faster, more efficient, and more scalable cache coherence schemes than the existing ones. In this paper we present a new scheme that has a potential to meet such a demand. The software support for our scheme is in the form of program annotations to detect shared accesses as well as release synchronizations that represent data sharing boundaries. A small hard-ware called Coherence Buffer (CB) with an associated controller, local to each processor forms the control unit to locally enforce cache coherence actions which are off the critical path. Our simulation study shows that a 8 entry 4-way associative CB helps achieve a speedup of 1.07 - 4.31 over full-map 3-hop directory scheme for five of the SPLASH-2 benchmarks (representative of migratory sharing, producer-consumer and write-many workloads), under Release Consistency model. |
Year | Venue | Keywords |
|---|---|---|
2002 | Euro-Par | global control,hardware-software approach,scalable cache coherence scheme,release consistency model,migratory sharing,enforcing cache coherence,associated controller,coherence buffer,splash-2 benchmarks,cache coherence action,application trend,research note,new scheme,3-hop directory scheme,cache coherence |
Field | DocType | ISBN |
Cache invalidation,Computer science,MESIF protocol,Parallel computing,MESI protocol,Cache algorithms,Bus sniffing,Speedup,Distributed computing,Cache coherence,Release consistency | Conference | 3-540-44049-6 |
Citations | PageRank | References |
1 | 0.35 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. Sarojadevi | 1 | 3 | 1.43 |
| S. K. Nandy | 2 | 320 | 50.83 |
| S. Balakrishnan | 3 | 5 | 1.65 |