Title
FPGA design methodology for a wavelet-based scalable video decoder
Abstract
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of advantages but the corresponding decoding algorithm is complex and really stresses the system bandwidth as it replaces the blockbased DCT-approach with frame-based wavelets. This has a tremendous impact on the hardware architecture.We present the implementation of the RESUME decoder using reconfigurable hardware designed through the use of state-of-the-art HW/SW-codesign techniques. These techniques were augmented with automatic loop transformations and regression testing. Our efforts resulted in a design capable of decoding more than 25 frames per second at lossless CIF resolution.
Year
DOI
Venue
2007
10.1007/978-3-540-73625-7_19
SAMOS
Keywords
Field
DocType
sw-codesign technique,reconfigurable hardware,wavelet-based scalable video decoder,efficient decoding,client-side diversification,corresponding decoding algorithm,resume decoder,frame-based wavelet,automatic loop transformation,hardware architecture,fpga design methodology,blockbased dct-approach,frames per second,design methodology,regression testing
Common Intermediate Format,Computer science,Frame rate,Discrete wavelet transform,Decoding methods,Computer hardware,Video decoder,Lossless compression,Embedded system,Reconfigurable computing,Scalability
Conference
Volume
ISSN
ISBN
4599
0302-9743
3-540-73622-0
Citations 
PageRank 
References 
0
0.34
3
Authors
5
Name
Order
Citations
PageRank
Hendrik Eeckhaut1513.95
Harald Devos2347.10
Philippe Faes3202.43
Mark Christiaens414912.79
dirk stroobandt5833101.36