Name
Abstract | ||
|---|---|---|
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. Despite a recent surge in interest in three-dimensional graphics from computer architects, high-quality high-speed texture mapping has so far been confined to costly hardware systems that use brute-force techniques to achieve high performance. One obstacle faced by designers of texture mapping systems is the requirement of extremely high bandwidth to texture memory. High bandwidth is necessary since there are typically tens to hundreds of millions of accesses to texture memory per second. In addition, to achieve the high clock rates required in graphics pipelines, low-latency access to texture memory is needed. In this paper, we propose the use of texture image caches to alleviate the above bottlenecks, and evaluate various tradeoffs that arise in such designs.We find that the factors important to cache behavior are (i) the representation of texture images in memory, (ii) the rasterization order on screen and (iii) the cache organization. Through a detailed investigation of these issues, we explore the best way to exploit locality of reference and determine whether this technique is robust with respect to different scenes and different amounts of texture. Overall, we observe that there is a significant amount of temporal and spatial locality and that the working set sizes are relatively small (at most 16KB) across all cases that we studied. Consequently, the memory bandwidth requirements of a texture cache system are substantially lower (at least three times and as much as fifteen times) than the memory bandwidth requirements of a system which achieves equivalent performance but does not utilize a cache. These results are very encouraging and indicate that caching is a promising approach to designing memory systems for texture mapping. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1145/264107.264152 | Denver, Colorado, USA |
Keywords | Field | DocType |
instruction level parallelism,layout,computer graphics,pipelines,dynamic compilation,low latency,surface texture,computer architecture,hardware,real time,texture mapping,memory bandwidth,superscalar,bandwidth | Texture mapping,Mipmap,Locality of reference,Computer science,Cache,Parallel computing,Cache-only memory architecture,Real-time computing,Texture memory,Cache coloring,Non-uniform memory access | Conference |
Volume | Issue | ISSN |
25 | 2 | 0163-5964 |
ISBN | Citations | PageRank |
0-89791-901-7 | 85 | 11.52 |
References | Authors | |
14 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ziyad S. Hakura | 1 | 130 | 16.50 |
| Anoop Gupta | 2 | 6610 | 867.50 |