Name
Abstract | ||
|---|---|---|
Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1016/j.microrel.2003.07.001 | Microelectronics Reliability |
Keywords | Field | DocType |
strain energy density,wireless communication,thermal cycling,flip chip,chip | Flip chip,Wire bonding,Surface-mount technology,Electronic engineering,Soldering,Temperature cycling,Thermal copper pillar bump,Engineering,Interconnection,Photodiode | Journal |
Volume | Issue | ISSN |
44 | 1 | 0026-2714 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K.S. Kim | 1 | 2 | 2.74 |
| H.I. Kim | 2 | 0 | 0.34 |
| C.H. Yu | 3 | 0 | 0.34 |
| E.G. Chang | 4 | 4 | 1.43 |