Paper Info
Title
Hardware Integrated Quantization Solution For Improvement Of Computational H.264 Encoder Module
Abstract
The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamard and Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.
Year
DOI
Venue
2010
10.1109/VLSISOC.2010.5642680
PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP
Keywords
Field
DocType
DCT, Hadamard, Quantization, H.264 encoder, FPGA
Computer science,Discrete cosine transform,Field-programmable gate array,Redundancy (engineering),Encoder,VHDL,Computer hardware,Quantization (signal processing),Hadamard transform,Hardware description language
Conference
Citations 
PageRank 
References 
6
0.53
5
Authors
6
Name
Order
Citations
PageRank
Ronaldo Husemann1195.74
Mariano Majolo2111.73
Victor Guimaraes360.53
Altamiro Amadeu Susin432937.42
Valter Roesler53611.96
José Valdeni de Lima610718.91