Paper Info
Title
Scalable multi-cores with improved per-core performance using off-the-critical path reconfigurable hardware
Abstract
Scaling the number of cores in a multi-core processor constraintsthe resources available in each core, resulting in reduced percoreperformance. Alternatively, the number of cores have to be reducedin order to improve per-core performance. In this paper, we propose atechnique to improve the per-core performance in a many-core processorwithout reducing the number of cores. In particular, we integrate aReconfigurable Hardware Unit (RHU) in each core. The RHU executesthe frequently encountered instructions to increase the core's overall executionbandwidth, thus improving its performance. We also propose anovel integrated hardware/software methodology for efficient RHU reconfiguration.The RHU has low area overhead, and hence has minimalimpact on the scalability of the multi-core. Our experiments show thatthe proposed architecture improves the per-core performance by an averageof about 12% across a wide range of applications, while incurringa per-core area overhead of only about 5%.
Year
DOI
Venue
2008
10.1007/978-3-540-89894-8_33
HiPC
Keywords
Field
DocType
scalable multi-cores,per-core performance,many-core processorwithout,off-the-critical path reconfigurable hardware,anovel integrated hardware,areconfigurable hardware unit,low area overhead,multi-core processor constraintsthe resource,incurringa per-core area overhead,efficient rhu reconfiguration,rhu executesthe,improved per-core performance,overall executionbandwidth,systems biology,mutual information,reconfigurable hardware,critical path,gene networks,multi core processor
Computer science,Parallel computing,Software,Critical path method,Reconfigurable computing,Distributed computing,Scalability
Conference
Volume
ISSN
Citations 
5374
0302-9743
1
PageRank 
References 
Authors
0.35
27
2
Name
Order
Citations
PageRank
Tameesh Suri1495.44
Aneesh Aggarwal220216.91