Name
Title | ||
|---|---|---|
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter |
Abstract | ||
|---|---|---|
This paper proposes a 55 nm CMOS 12-bit current-steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/JSSC.2012.2191331 | J. Solid-State Circuits |
Keywords | Field | DocType |
spurious free dynamic range,analog circuits,cmos integrated circuits,finger separating,finger splitting,po mode,frequency 1 mhz,power efficiency improvement,least significant bit,dual-dvs control,finger shifting,transient state,area efficiency,sido converter,inl,digital circuits,cross-regulation performance,high definition video dac performance,dnl performance,integral nonlinearity,differential nonlinearity (dnl),sfdr,3s method,voltage 1 v,size 55 nm,lsb,single-inductor dual-output switching converter,cmos current-steering video digital-to-analog converter,single-inductor dual-output (sido),spurious free dynamic range (sfdr),steady state,integral nonlinearity (inl),interference suppression,power optimized mode,embedded dynamic voltage scaling system,energy efficiency,dynamic voltage scaling (dvs),differential nonlinearity performance,switching noise interference suppression,digital to analog converter (dac),word length 12 bit,digital-analogue conversion,least significant bit (lsb),power consumption reduction,dc-dc converter,energy efficient,power efficiency,power optimization,noise,layout | Dynamic voltage scaling,Electrical efficiency,Integral nonlinearity,Analogue electronics,Differential nonlinearity,Computer science,CMOS,Spurious-free dynamic range,Electronic engineering,Digital-to-analog converter | Journal |
Volume | Issue | ISSN |
47 | 7 | 0018-9200 |
Citations | PageRank | References |
2 | 0.48 | 15 |
Authors | ||
13 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-shen Chou | 1 | 8 | 1.87 |
| Tzu-Chi Huang | 2 | 95 | 19.64 |
| Yu-Huei Lee | 3 | 104 | 19.53 |
| Yao-Yi Yang | 4 | 41 | 7.49 |
| Yi-Ping Su | 5 | 55 | 7.88 |
| Ke-Horng Chen | 6 | 379 | 90.04 |
| Chen-Chih Huang | 7 | 74 | 14.67 |
| Ying-Hsi Lin | 8 | 112 | 30.84 |
| Chao-Cheng Lee | 9 | 86 | 18.59 |
| Kuei-Ann Wen | 10 | 80 | 16.55 |
| Ying-Chih Hsu | 11 | 4 | 1.23 |
| Yung-Chow Peng | 12 | 10 | 2.86 |
| Fu-Lung Hsueh | 13 | 98 | 13.23 |