Name
Abstract | ||
|---|---|---|
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1093/ietisy/e88-d.7.1646 | Ieice Transactions |
Keywords | DocType | Volume |
partial order reduction,safety failure,timing failures,detecting safety,original untimed trace theory,partial order reduction algorithm,timing failure,trace theoretic verification,hierarchical structure,dme circuit,timed circuits,conformance checking | Journal | E88-D |
Issue | ISSN | Citations |
7 | 0302-9743 | 6 |
PageRank | References | Authors |
0.48 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Denduang Pradubsuwun | 1 | 6 | 0.48 |
| Tomohiro Yoneda | 2 | 353 | 41.62 |
| Chris Myers | 3 | 72 | 10.44 |