Name
Abstract | ||
|---|---|---|
This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-44614-1_10 | FPL |
Keywords | Field | DocType |
time-multiplexed execution,synchronous circuit,separated context,hardware resource,fipsoc devices,virtual circuits,dynamic reconfigurable,dynamic reconfiguration,systematic technique,virtual circuit,temporal bipartitioning rule,fipsoc device | Sequential logic,Computer science,Field-programmable gate array,Real-time computing,Synchronous circuit,Virtual circuit,Control reconfiguration | Conference |
ISBN | Citations | PageRank |
3-540-67899-9 | 0 | 0.34 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Cantó | 1 | 37 | 3.46 |
| Juan Manuel Moreno | 2 | 186 | 32.74 |
| joan cabestany | 3 | 1276 | 143.82 |
| I. Lacadena | 4 | 0 | 0.34 |
| Josep Maria Insenser | 5 | 19 | 3.02 |