Name
Title | ||
|---|---|---|
Efficient hardware solution for practical intra h.264/SVC video encoder implementation |
Abstract | ||
|---|---|---|
The emergent standard H.264/SVC (scalable video coding) combines distinct complex techniques in order to allow efficient data compression considering data among consecutive layers. In practice, a complete implementation of this scalable encoder is not trivial, since the global complexity increases proportionally with the number of layers involved. Considering that, this paper proposes an innovative scalable architecture, which adopts a flexible approach able to reuse computational hardware modules in order to perform iteratively the SVC intra computational coding, for both the base layer and enhancement layers. In order to validate this proposal it was implemented in VHDL and compared with other conventional hardware approaches, confirming significant gain in terms of occupied memory and total chip area. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2020876.2020908 | SBCCI |
Keywords | Field | DocType |
computational hardware module,consecutive layer,scalable video coding,conventional hardware approach,svc intra computational coding,scalable encoder,innovative scalable architecture,practical intra h,complete implementation,efficient hardware solution,base layer,svc video encoder implementation,efficient data,programmable logic,data compression,fpga,chip | Computer science,Field-programmable gate array,Real-time computing,Coding (social sciences),Encoder,VHDL,Computer hardware,Data compression,Scalable Video Coding,Scalability,Programmable logic device | Conference |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ronaldo Husemann | 1 | 19 | 5.74 |
| Altamiro Amadeu Susin | 2 | 329 | 37.42 |
| Valter Roesler | 3 | 36 | 11.96 |
| José Valdeni de Lima | 4 | 107 | 18.91 |