Name
Abstract | ||
|---|---|---|
A wide loop bandwidth in fractional-N PLL is desirable for good jitter performance. However, a wider bandwidth reduces the effective oversampling ratio between update rate and loop bandwidth, making quantization error a much bigger noise contributor. A successful implementation of a wideband frequency synthesizer is in managing jitter and spurious performance. In this paper we present a new PLL architecture for bandwidth extension. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single reference cycle and utilized for phase update, thereby effectively forming a reference multiplier. This enables a higher oversampling ratio for better quantization noise shaping and makes a wideband fractional-N PLL possible. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1142/S0218126612400105 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
PLL,synthesizer,fractional-N,delta sigma,noise shaping | Wideband,Phase-locked loop,Oversampling,Computer science,Bandwidth extension,PLL multibit,Electronic engineering,Bandwidth (signal processing),Jitter,Direct digital synthesizer | Journal |
Volume | Issue | ISSN |
21 | 6 | 0218-1266 |
Citations | PageRank | References |
2 | 0.38 | 2 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiao Pu | 1 | 5 | 1.56 |
| Krishnaswamy Nagaraj | 2 | 40 | 14.10 |
| J. Abraham | 3 | 4905 | 608.16 |
| Axel Thomsen | 4 | 3 | 3.80 |