Name
Abstract | ||
|---|---|---|
This paper presents an approach and test sequence to detect inter-port bridging faults in dual-port memories. Unlike other approaches we model a fault as a four-way bridging fault which is more reflective of a real defect. In our test approach, we consider word- and bit- line bridges, both in structure and in functional modes. Further, faults for all scenarios namely, read-read, write-write, and read-write ports are considered. We also propose the use of additional logic, three wide-OR gates, to detect certain inter-port faults that may remain undetected otherwise. Our approach achieves 100% coverage of all inter-port bridging faults. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ISCAS.2010.5537500 | ISCAS |
Keywords | Field | DocType |
word-line bridges,logic circuits,bit-line bridges,read-write ports,inter-port bridging faults detection,wide-or gates,detect inter-port bridging faults,write-write ports,dual-port memories,test sequence,fault location,four-way bridging fault,read-read ports,logic gates,inter-port faults,computational modeling,testing | Port (computer networking),Logic gate,Bridging fault,Computer science,Test sequence,Bridging (networking),Electronic engineering | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4244-5309-2 | 0 |
PageRank | References | Authors |
0.34 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ho-yong Choi | 1 | 7 | 3.00 |
| Kewal K. Saluja | 2 | 1483 | 141.49 |