Name
Abstract | ||
|---|---|---|
Abstract: This paper presents a semi-synchronous pipeline scheme, here referred as single-pulse pipeline, to the problem of mapping pipelined circuits to a Field Programmable Gate Arra (FPGA).Area and timing considerations are given for a general case and later applied to a systolic circuit as illustration. The single-pulse pipeline can manage asynchronous worst-case data completion and it is evaluated against two chosen asynchronous pipelining: a four-phase bundle-data pipeline and a doubly-latched asynchronous pipeline. The semi-synchronous pipeline proposal takes less FPGA area and operates faster than the two selected fully-asynchronous schemes for an FPGA case. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/DSD.2001.952298 | Warsaw |
Keywords | Field | DocType |
fpga case,fpga area,pipelining considerations,asynchronous pipelining,single-pulse pipeline,semi-synchronous pipeline proposal,four-phase bundle-data pipeline,doubly-latched asynchronous pipeline,semi-synchronous pipeline scheme,asynchronous worst-case data completion,general case,fpga,field programmable gate arrays,logic design,computer aided software engineering,quantization,computer science,field programmable gate array,circuits | Logic synthesis,Pipeline (computing),Asynchronous communication,Computer architecture,Computer science,Programmable logic array,Field-programmable gate array,Real-time computing,Electronic circuit | Conference |
ISBN | Citations | PageRank |
0-7695-1239-9 | 4 | 0.53 |
References | Authors | |
8 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oswaldo Cadenas | 1 | 14 | 5.38 |
| Graham Megson | 2 | 13 | 4.03 |