Name
Title | ||
|---|---|---|
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks |
Abstract | ||
|---|---|---|
A key aspect in the design of efficient multiprocessor systems is the cache coherence protocol. Although directory-based protocols constitute the most scalable approach, the limited size of the directory caches together with the growing size of systems may cause frequent evictions and, consequently, the invalidation of cached blocks, which jeopardizes system performance. Directory caches keep track of every memory block stored in processor caches in order to provide coherent access to the shared memory. However, a significant fraction of the cached memory blocks do not require coherence maintenance (even in parallel applications) because they are either accessed by just one processor or they are never modified. In this paper, we propose to deactivate the coherence protocol for those blocks that do not require coherence. This deactivation means directory caches do not have to keep track of noncoherent blocks, which reduces directory cache occupancy and increases its effectiveness. Since the detection of noncoherent blocks is carried out by the operating system, our proposal only requires minor hardware modifications. Simulation results show that, thanks to our proposal, directory caches can avoid the tracking of about 66 percent (on average) of the blocks accessed by a wide range of applications, thereby improving the efficiency of directory caches. This contributes either to shortening the runtime of parallel applications by 15 percent (on average) while keeping directory cache size or to maintaining performance while using directory caches 16 times smaller. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TC.2011.241 | IEEE Trans. Computers |
Keywords | Field | DocType |
coherence maintenance,directory cache occupancy,limited size,parallel application,noncoherent block,directory cache,cache coherence protocol,noncoherent memory blocks,directory cache size,cached memory block,coherence protocol,directory caches,maintenance engineering,memory management,strontium,operating system,coherence,hardware,protocols,multiprocessor,cache coherence,parallel processing | Shared memory,CPU cache,Computer science,Directory,Cache,Parallel computing,Multiprocessing,Real-time computing,Memory management,Bus sniffing,Operating system,Cache coherence | Journal |
Volume | Issue | ISSN |
62 | 3 | 0018-9340 |
Citations | PageRank | References |
15 | 0.57 | 24 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Blas Cuesta | 1 | 43 | 3.58 |
| Alberto Ros | 2 | 384 | 32.60 |
| Maria E. Gomez | 3 | 44 | 3.80 |
| Antonio Robles | 4 | 481 | 30.40 |
| Jose Duato | 5 | 893 | 54.65 |