Name
Abstract | ||
|---|---|---|
Two synchronous multiprocessor architectures based on pipelined optical bus interconnections are presented. The first is a linear pipeline with enhanced control strategies which make optimal use of the available communication bandwidth of the optical bus. The second is a two-dimensional architecture in which processors are placed in a square grid and interconnected to one another through horizontal and vertical pipelined optical buses. These architectures allow any two processors to communicate with each other using one (for the linear case) or two (for the two-dimensional case) pipelined bus cycles. Further, they permit all processors to have simultaneous access to the buses using slots within a pipelined cycle. We show that the architectures have simple control structures and that well-known processor interconnections, e.g., the complete binary trees and the hypercube networks, can be efficiently embedded in them. These architectures have an effectively higher bandwidth than conventional bus configurations and appear to be good candidates for a new generation of hybrid optical-electronic parallel computers. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1016/0743-7315(91)90130-2 | J. Parallel Distrib. Comput. |
Keywords | Field | DocType |
pipelined communication | Computer science,Parallel computing,Binary tree,Multiprocessing,Bandwidth (signal processing),Control system,Systems architecture,Interconnection,Hypercube,System bus | Journal |
Volume | Issue | ISSN |
12 | 3 | Journal of Parallel and Distributed Computing |
Citations | PageRank | References |
70 | 3.21 | 21 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zicheng Guo | 1 | 226 | 18.35 |
| Rami G. Melhem | 2 | 528 | 34.60 |
| Richard W. Hall | 3 | 220 | 25.71 |
| Donald M. Chiarulli | 4 | 213 | 24.91 |
| Steven P. Levitan | 5 | 288 | 60.98 |