Paper Info
Title
A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects
Abstract
Current mode signaling(CMS) scheme is one of the promising alternatives to voltage mode buffer insertion scheme for high-speed low-power data transmission over long on-chip interconnects. In this paper we present a CMS scheme with dynamic overdriving driver (DOD) whose performance is robust against intra-die and inter-die process variations. We show that throughput of the CMS scheme proposed in [1] degrades by 33% in the presence of intra-die process variations whereas that of the scheme in [2] degrades by 36% in the worst case process corner. Simulation results show that throughput of the proposed CMS scheme degrades by only 9.5% in presence of intra-die process variations and 22% in the worst case process corner. In this process corner, logic speed itself degrades by 23% and hence 22% of throughput degradation of the proposed signaling scheme is not a major concern. In the typical process corner, the proposed CMS scheme shows 14% and 19% improvement in delay and power, respectively over CMS scheme proposed in [1].
Year
DOI
Venue
2009
10.1145/1531542.1531630
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
process variation tolerant,inter-die process variation,worst case process corner,low-power current mode,throughput degradation,mode buffer insertion scheme,cms scheme,proposed cms scheme degrades,intra-die process variation,process corner,on-chip interconnects,typical process corner,proposed cms scheme shows,data transmission,chip,process variation
Throughput degradation,Data transmission,Process corners,Computer science,Voltage,Electronic engineering,Real-time computing,Process variation,Throughput,Current mode
Conference
Citations 
PageRank 
References 
5
0.64
2
Authors
3
Name
Order
Citations
PageRank
Marshnil Vipin Dave1111.27
Maryam Shojaei Baghini28629.67
Dinesh Kumar Sharma34811.91