Abstract | ||
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This paper presents a way to contract timed STGs effectively for a decomposition based logic synthesis of timed circuits. In the decomposition based synthesis method, a sufficient input signal set for each output is first obtained, and the timed STG is contracted to include only transitions on this input signal set and the output of interest, from which the circuit for the output is synthesized. Care is, however, needed for the contraction of timed STGs. A simple contraction algorithm used for the untimed version can result in the loss of important timing information, causing it to synthesize non-optimal circuits. On the other hand, exact contraction that preserves the timing information precisely is applied only to a small class of transitions, which degrades the performance of the decomposition based synthesis method. This paper proposes a way to contract timed STGs effectively without losing the optimality of the synthesized circuits, and shows some experimental results. |
Year | DOI | Venue |
---|---|---|
2006 | 10.1007/11901914_19 | ATVA |
Keywords | Field | DocType |
sufficient input signal,exact contraction,simple contraction algorithm,important timing information,synthesized circuit,circuit synthesis,effective contraction,timing information,input signal set,logic synthesis,synthesis method | Logic synthesis,Logic gate,Computer science,Discrete cosine transform,Algorithm,Circuit design,Decomposition method (constraint satisfaction),Electronic circuit,Asynchronous circuit | Conference |
Volume | ISSN | ISBN |
4218 | 0302-9743 | 3-540-47237-1 |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Tomohiro Yoneda | 1 | 353 | 41.62 |
Chris J. Myers | 2 | 607 | 75.73 |