Name
Abstract | ||
|---|---|---|
In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillatior output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs; in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 mus for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9degrees rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/TCSII.2003.820250 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Keywords | DocType | Volume |
direct digital synthesizer (DDS), frequency synthesis, phase-locked loop (PLL), phase noise, wireless communication | Journal | 50 |
Issue | ISSN | Citations |
12 | 1549-7747 | 4 |
PageRank | References | Authors |
0.65 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andrea Bonfanti | 1 | 269 | 36.37 |
| F. Amorosa | 2 | 4 | 0.65 |
| C. Samori | 3 | 241 | 26.26 |
| A. L. Lacaita | 4 | 151 | 18.16 |