Name
Abstract | ||
|---|---|---|
This paper presents a new Fault Simulator architecturefor RAM memories. The key features of the proposed toolare: 1) user-definable fault models, test algorithm, andmemory architecture; 2) very fast simulation algorithm; 3)ability to compute the coverage of any provided testsequence w.r.t. a user-defined set of fault models, and toeliminate redundant operations; 4) assessment of thepower consumption generated by the test application.Moreover, the tool is able to modify the test algorithm inorder to guarantee the compliance to user-defined powerconsumption constraints. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ATS.2002.1181693 | Asian Test Symposium |
Keywords | Field | DocType |
fault simulator,andmemory architecture,test algorithm inorder,ram memory,test algorithm,user-defined powerconsumption constraint,fault model,new memory,user-definable fault model,user-defined set,test application,simulation algorithm,logic simulation | Stuck-at fault,Automatic test pattern generation,Segmentation fault,Computer science,Read-write memory,Real-time computing,Electronic engineering,Page fault,Fault Simulator,Fault model,Memory architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-1825-7 | 16 | 1.05 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Benso | 1 | 148 | 12.69 |
| S. Di Carlo | 2 | 128 | 9.63 |
| G. Di Natale | 3 | 111 | 8.87 |
| P. Prinetto | 4 | 516 | 55.23 |