Name
Title | ||
|---|---|---|
FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon Codes |
Abstract | ||
|---|---|---|
This paper presents an FPGA implementation of a high-speed interpolation processor for algebraic soft-decision decoding of Reed-Solomon codes. In the design, pipelining and parallel processing techniques are exploited to increase the decoding throughput. In addition, different parts of the interpolation processor are properly scheduled to achieve maximum overlap in processing time for the computations occurring at adjacent iterations. Synthesis results show that the FPGA implementation of the interpolation architecture can achieve a throughput of 149Mbps, which is multiple times higher than conventional design. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378513 | ISCAS |
Keywords | Field | DocType |
parallel processing,interpolation processor,149 mbit/s,microprocessor chips,soft-decision decoding,interpolation,parallel processing techniques,reed-solomon codes,fpga implementation,field programmable gate arrays,adjacent iterations,interpolation architecture,polynomials,throughput,galois fields,reed solomon code,computer architecture,engines | Pipeline (computing),Finite field,Polynomial,Computer science,Parallel computing,Interpolation,Field-programmable gate array,Electronic engineering,Reed–Solomon error correction,Decoding methods,Throughput | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 2 |
PageRank | References | Authors |
0.46 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qinqin Chen | 1 | 10 | 3.11 |
| Zhongfeng Wang | 2 | 241 | 19.02 |
| Jun Ma | 3 | 93 | 9.42 |