Name
Abstract | ||
|---|---|---|
In this paper, we present the design of a GALS wrapper used in Network on Chip (NoC) based on standard cells. The GALS wrapper includes two communication ports, 4-phase handshake circuits, data buffer and signal synchronizer. The detailed design methodology of GALS wrapper is given and the circuits are validated with Verilog-HDL and implemented in FPGA. The simulation results show that the wrapper provides fast and reliable asynchronous communication services for the subsystems working with different clocks in NoC. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CSIE.2009.520 | CSIE (3) |
Keywords | Field | DocType |
data buffer,4-phase handshake circuit,detailed design methodology,standard cell,simulation result,signal synchronizer,gals wrapper,communication port,different clock,reliable asynchronous communication service,network interfaces,protocols,system on a chip,design methodology,field programmable gate arrays,synchronizer,fpga,hardware description languages,network on chip,asynchronous communication,synchronization,logic design,data mining | Logic synthesis,Asynchronous communication,System on a chip,Synchronizer,Computer science,Network on a chip,Data buffer,Hardware description language,Network interface,Embedded system | Conference |
Citations | PageRank | References |
2 | 0.42 | 6 |
Authors | ||
3 | ||