Name
Title | ||
|---|---|---|
An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture |
Abstract | ||
|---|---|---|
With the continued development of RFID technology, a large number of RFID tags are being deployed having different protocols. Hence, a multiprotocol interrogator which can support all of these alternatives has become a design requirement for many systems. While multifunction capability may be implemented using a high performance DSP, CPU or FPGA, those solutions have a large area cost, so an innovative architecture is needed. Starting from an analysis of the algorithms in RFID systems, we propose a reconfigurable architecture for baseband processing to realize the various protocols in the ISO18000 standard. The structure has been specifically designed to support all of the functions needed, so that it performs very efficiently with low area cost. This design has been post-layout simulated with a clock frequency of up to 83 MHz, and the core area is 4 mm2 in a UMC 0.18 mum CMOS process. Compared with other existing processors, the proposed architecture is much more efficient for this application area. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICESS.2008.61 | ICESS |
Keywords | Field | DocType |
protocols,application area,iso18000 standard,innovative architecture,iso standards,efficient multiprotocol rfid interrogator baseband processor,microprocessor chips,multiprotocol interrogator,large area cost,rfid technology,low area cost,efficient multi-protocol rfid interrogator,reconfigurable architectures,proposed architecture,multifunction capability,baseband processor,reconfigurable baseband processor,radiofrequency identification,rfid system,baseband processing,rfid tags,reconfigurable architecture,design requirement,iso18000,core area,rfid,rfid tag,multi-protocol,cost function,compressors,correlation,finite impulse response filter,field programmable gate arrays,iso,baseband,digital signal processing,algorithm design and analysis | Digital signal processing,Baseband,Architecture,Algorithm design,Computer science,Field-programmable gate array,Real-time computing,Baseband processor,Finite impulse response,Clock rate,Embedded system | Conference |
ISSN | ISBN | Citations |
2576-3504 | 978-0-7695-3287-5 | 0 |
PageRank | References | Authors |
0.34 | 4 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuang Zhao | 1 | 2 | 1.77 |
| Wenqing Lu | 2 | 16 | 2.49 |
| Chao Lu | 3 | 1 | 1.03 |
| Xiaofang Zhou | 4 | 11 | 4.11 |
| Dian Zhou | 5 | 260 | 56.14 |
| Gerald E. Sobelman | 6 | 225 | 44.78 |