Name
Abstract | ||
|---|---|---|
Design guidelines for static and domino silicon-on-insulator (SOI) CMOS circuits are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-silicon. Most published design fixes for eliminating parasitic bipolar induced upset are shown to aggravate the charge sharing problem. A new and improved predischarge method for enhancing the noise tolerance of SOI domino circuits is thus proposed. The topic of multiple output domino logic in SOI technology is addressed for the first time. Multiple output domino logic is shown to be more prone to bipolar leakage induced upset than regular domino. Many of the design practices used to alleviate bipolar leakage in regular domino are no longer valid due to the multiple output domino logic's inherent design requirements. A novel SOI-specific multiple output domino logic, particularly suitable for adder designs, is introduced to minimize the bipolar leakage risk. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/TVLSI.2004.833665 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
design fix,domino silicon-on-insulator,adder design,soi technology,critical evaluation,design guideline,multiple output domino logic,soi domino circuit,bipolar leakage,regular domino,bipolar leakage risk,soi design guideline,adder,logic design,adders,silicon,noise factor,cmos technology,logic circuit,logic gates,implementation,integrated circuit,leakage current,silicon on insulator,waveform,integrated circuit design,si | Logic synthesis,Domino logic,Logic gate,Adder,Computer science,Electronic engineering,CMOS,Charge sharing,Domino,Integrated circuit design | Journal |
Volume | Issue | ISSN |
12 | 9 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rouwaida Kanj | 1 | 262 | 29.95 |
| Elyse Rosenbaum | 2 | 61 | 21.99 |