Abstract | ||
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Developers of next generation Multi-Processor Systems-on-a-chip (MPSoC) silicon platforms used in multimedia mobile devices should design efficient systems for diverse execution time vs. energy consumption trade-offs for a given quality of service. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can obtain singular computational/power trades offs points and thus design energy efficient platforms. This paper presents a high level methodology to acquire an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a MPEG-4 encoder described in C++ language which is translated to a SystemC hard/soft description which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (CRISP-Trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a classic DSP. |
Year | DOI | Venue |
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2006 | 10.1109/SOCC.2006.283833 | SoCC |
Keywords | Field | DocType |
research framework,field programmable gate arrays,energy efficient,asic,system on chip,system on a chip,dsp,functional unit,processor architecture,mobile device,application specific integrated circuits,quality of service | System on a chip,Computer science,Field-programmable gate array,Electronic engineering,Application-specific integrated circuit,SystemC,Real-time computing,Frequency scaling,Encoder,MPSoC,Energy consumption,Embedded system | Conference |
ISSN | ISBN | Citations |
2164-1676 | 0-7803-9782-7 | 0 |
PageRank | References | Authors |
0.34 | 2 | 7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Antoni Portero | 1 | 43 | 8.87 |
Guillermo Talavera | 2 | 47 | 4.00 |
Marius Monton | 3 | 18 | 4.23 |
Borja Martinez | 4 | 210 | 17.65 |
Marc Moreno | 5 | 0 | 0.34 |
Francky Catthoor | 6 | 3932 | 423.30 |
Jordi Carrabina | 7 | 139 | 36.98 |