Name
Abstract | ||
|---|---|---|
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium(r) Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25m CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400MHz clocked circuit. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ASYNC.1999.761523 | ASYNC |
Keywords | Field | DocType |
asynchronous instruction length decoder,processor instruction decoder,clocked circuit,intel architecture,cmos process,aggressive asynchronous design methodology,rappid chip,potential advantage,revolving asynchronous pentium,design technology,ns-with manageable risk,risk management,chip,throughput,low power electronics,latency,prototypes,cmos technology,design methodology,decoding,technology management,integrated circuit design | Asynchronous communication,Computer science,Chip,CMOS,Integrated circuit design,Pentium,Throughput,Decoding methods,Low-power electronics,Embedded system | Conference |
ISSN | ISBN | Citations |
1522-8681 | 0-7695-0031-5 | 43 |
PageRank | References | Authors |
3.58 | 6 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shai Rotem | 1 | 102 | 7.33 |
| Ken Stevens | 2 | 58 | 4.91 |
| Charles Dike | 3 | 43 | 3.58 |
| Marly Roncken | 4 | 298 | 63.79 |
| Boris Agapiev | 5 | 43 | 3.58 |
| Ran Ginosar | 6 | 1410 | 135.61 |
| Rakefet Kol | 7 | 56 | 5.12 |
| Peter Beerel | 8 | 44 | 4.29 |
| Chris J. Myers | 9 | 607 | 75.73 |
| Kenneth Yun | 10 | 52 | 5.61 |