Name
Title | ||
|---|---|---|
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip |
Abstract | ||
|---|---|---|
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power implications, but gives rise to a well-differentiated point in the architecture design space. This in an effect of the tight interaction existing between architecture and physical design layers in nanoscale technologies. This work assesses several NoC link inference techniques (buffering options, link pipelining) by means of commercial backend synthesis tools, taking the system-level perspective. In fact, performance speed-ups and power overhead are not evaluated for the links in isolation but for the network topology as a whole, thus showing their sensitivity to the link inference strategy. k-ary n-mesh topologies are considered for the sake of analysis, in that they provide a range of topologies with increasing total wirelength. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1531542.1531574 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
topology-level implication,local performance,commercial backend synthesis tool,nanoscale networks-on-chip,noc link inference technique,link inference strategy,link synthesis technique,nanoscale technology,link implementation solution,performance speed-up,architecture design space,link pipelining,network on chip,network topology | Architecture design,Pipeline (computing),Architecture,Computer science,Inference,Network on a chip,Electronic engineering,Network topology,Real-time computing,Physical design | Conference |
Citations | PageRank | References |
4 | 0.45 | 23 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniele Ludovici | 1 | 61 | 4.92 |
| Georgi Gaydadjiev | 2 | 1117 | 104.92 |
| Davide Bertozzi | 3 | 1653 | 99.83 |
| Luca Benini | 4 | 13116 | 1188.49 |