Name
Abstract | ||
|---|---|---|
LDPC coding has attracted much attention due to its high performance, and it has been widely used in telecommunication systems. This paper focuses on the decoder hardware architecture, especially on memory size reduction, which is an important part of the entire area cost. The design has been post-layout simulated using a UMC 0.18 micron technology at a clock speed of 74 MHz. Using the proposed 3-level memory structure together with the described control logic, the required number of bits of memory can be reduced by up to 34.9% compared to prior approaches. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/APCCAS.2010.5774863 | APCCAS |
Keywords | Field | DocType |
ldpc,decoder,low density parity check code,micron technology,ldpc layered decoders,memory size reduction,hierarchical memory organization,memory architecture,control logic,layered decoding,parity check codes,decoder hardware architecture,telecommunication systems,registers,ldpc code,hardware architecture,memory management,decoding | Computer science,Low-density parity-check code,Parallel computing,Electronic engineering,Coding (social sciences),Memory management,Control logic,Decoding methods,Computer hardware,Clock rate,Memory architecture,Hardware architecture | Conference |
Volume | Issue | ISBN |
null | null | 978-1-4244-7454-7 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuang Zhao | 1 | 2 | 1.77 |
| Xiaofang Zhou | 2 | 11 | 4.11 |
| Fanglong Ying | 3 | 0 | 0.34 |
| Gerald E. Sobelman | 4 | 225 | 44.78 |