Name
Abstract | ||
|---|---|---|
Commercial design verification is a complex activity involving many abstraction levels (such as architectural, register transfer, gate, switch, circuit, fabrication), many different aspects of design (such as timing, speed, functional, power, reliability and manufactureability) and many different design styles (such as ASIC, full custom, semi-custom, memory, cores, and asynchronous). We present a representative design how and methodology that is common to many commercial integrated circuit design environments and that concentrates on functional validation using informal verification (e.g., simulation, emulation and ATPG) and formal verification (e.g, logic checking and sequential verification). |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/TEST.1996.557145 | ITC |
Keywords | Field | DocType |
commercial design verification,random processes,application specific integrated circuits,manufacturing,integrated circuit design,formal verification,atpg,simulation,fabrication,emulation,design for testability,design methodology,registers,design flow,switches,computational complexity | Formal equivalence checking,Computer architecture,Functional verification,Computer science,Intelligent verification,Physical verification,Runtime verification,Verification,Electronic engineering,Physical design,High-level verification | Conference |
ISBN | Citations | PageRank |
0-7803-3541-4 | 12 | 1.22 |
References | Authors | |
16 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carl Pixley | 1 | 418 | 44.09 |
| Noel R. Strader | 2 | 12 | 1.89 |
| W. C. Bruce | 3 | 22 | 5.87 |
| Jaehong Park | 4 | 919 | 87.01 |
| Matt Kaufmann | 5 | 56 | 20.74 |
| Kurt Shultz | 6 | 14 | 2.18 |
| Michael Burns | 7 | 14 | 2.29 |
| Jai Kumar | 8 | 13 | 1.60 |
| Jun Yuan | 9 | 13 | 3.60 |
| Janet Nguyen | 10 | 12 | 1.22 |