Paper Info
Title
Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving
Abstract
Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration of a Bit Manipulation Unit (BMU) [2] in an Altera NIOS-2 soft processor architecture [3] allows very interesting speed-up and power saving factors.
Year
DOI
Venue
2012
10.1109/ACSSC.2012.6489268
Signals, Systems and Computers
Keywords
DocType
ISSN
electronic engineering computing,embedded systems,microprocessor chips,Altera NIOS-2 soft processor architecture,BMU,bit manipulation unit,data wordlength,hardware accelerators,inverse butterfly net integration,software functions,standard microprocessors
Conference
1058-6393
ISBN
Citations 
PageRank 
978-1-4673-5050-1
0
0.34
References 
Authors
3
6
Name
Order
Citations
PageRank
Gian-carlo Cardarilli111020.75
Luca Di Nunzio2119.61
Rocco Fazzolari3119.36
Marco Re419435.03
Ruby Lee52460261.28
Di Nunzio, L.6103.53