Paper Info
Title
Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)
Abstract
Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12×12mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.
Year
DOI
Venue
2008
10.1016/j.microrel.2007.05.009
Microelectronics Reliability
Keywords
Field
DocType
thermal cycling,constitutive relation,mobile computer
Wafer,Wafer-level packaging,Printed circuit board,Electronic engineering,Redistribution layer,Soldering,Temperature cycling,Engineering,Chip-scale package,Fabrication
Journal
Volume
Issue
ISSN
48
4
0026-2714
Citations 
PageRank 
References 
0
0.34
10
Authors
5
Name
Order
Citations
PageRank
X.W. Zhang1328.97
Kripesh Vaidyanathan211.44
T.C. Chai3123.69
Teck Chun Tan400.34
D. Pinjala562.09