Paper Info
Title
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Abstract
Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.
Year
DOI
Venue
2008
10.1109/ETS.2008.13
European Test Symposium
Keywords
Field
DocType
capture-safe test generation scheme,low launch,high launch,effective capture-safety improvement,atpg flow,clocking scheme,switching-activity test generation,reliable capture-safety checking,at-speed scan testing,capture mode,practical capture-safe test generation,complete capture-safe test generation,switches,indium tin oxide,compaction,logic gates,automatic test pattern generation,testing
Automatic test pattern generation,Logic gate,Computer science,Timing error,Automatic testing,Electronic engineering,Real-time computing,Test compression,Circuit under test
Conference
ISSN
ISBN
Citations 
1530-1877
978-0-7695-3150-2
17
PageRank 
References 
Authors
0.83
12
11
Name
Order
Citations
PageRank
Wenyao Xu161577.06
K. Miyase21166.12
S. Kajihara343834.85
Hiroshi Furukawa421131.32
Y. Yamato5392.42
A. Takashima6170.83
K. Noda7170.83
H. Ito8170.83
Hatayama, K.9252.03
T. Aikyo10170.83
K. K. Saluja1134153.52