Abstract | ||
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Data locality optimization is a critical issue for NoC (network-on-chip) based multicore systems. In this paper, focusing on a two-dimensional NoC-based multicore and dataintensive multithreaded applications, we first discuss a data locality aware scheduling algorithm for any given computation-to-core mapping, and then propose an integrated mapping+scheduling algorithm that performs both tasks together. Both our algorithms consider temporal (time-wise) and spatial (neighborhood-aware) data reuse, and try to minimize distance-to-data in on-chip cache accesses. We test the effectiveness of our compiler algorithms using a set of twelve application programs. Our experiments indicate that the proposed algorithms achieve significant improvements in data access latencies (42.7% on average) and overall execution times (24.1% on average). We also conduct a sensitivity analysis where we change the number of cores, on-chip cache capacities, and data movement (migration) strategies. These experiments show that our proposed algorithms generate consistently good results.
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Year | DOI | Venue |
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2011 | 10.1109/CGO.2011.5764687 | CGO |
Keywords | Field | DocType |
scheduling algorithm,schedules,sensitivity analysis,synchronization,chip,data migration,multi threading,data access,multicore processing,network on chip | Locality,Cache,Computer science,Scheduling (computing),Parallel computing,Network on a chip,Real-time computing,Schedule,Data access,Multi-core processor,Data migration | Conference |
ISSN | ISBN | Citations |
2164-2397 | 978-1-61284-356-8 | 4 |
PageRank | References | Authors |
0.42 | 25 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Mahmut T. Kandemir | 1 | 7371 | 568.54 |
Yuanrui Zhang | 2 | 180 | 15.48 |
Jun Liu | 3 | 822 | 38.24 |
Taylan Yemliha | 4 | 36 | 3.76 |