Name
Abstract | ||
|---|---|---|
In this paper, a 3.125GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18μm CMOS process with a 1.8V supply. Behavioral simulations predict an 18% tuning range for the oscillator, with −91dBc/Hz phase noise at 1MHz offset. Its power consumption has been simulated to be as low as 15.3mW and the variation of its DC level of oscillation is 20mV, which corresponds to 1.3% of its mean value. While consuming less area than an LC VCO, the proposed oscillator design achieves a more stable and reliable operation point. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1016/j.microrel.2011.05.005 | Microelectronics Reliability |
Field | DocType | Volume |
Delay line oscillator,Oscillation,Variable-frequency oscillator,Phase noise,CMOS,Voltage-controlled oscillator,Vackář oscillator,Electronic engineering,Engineering,Pierce oscillator | Journal | 51 |
Issue | ISSN | Citations |
12 | 0026-2714 | 12 |
PageRank | References | Authors |
1.12 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carlis Sanchez-Azqueta | 1 | 35 | 14.63 |
| Santiago Celma | 2 | 145 | 43.45 |
| Francisco Aznar | 3 | 25 | 7.61 |