Name
Abstract | ||
|---|---|---|
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memories at 6.4 and 1.6 Gbps, respectively, with no package change. The interface is equipped with a compact voltage-mode driver with 1-tap pre-emphasis, in the WRITE direction, and a linear equalizer (LEQ) and 1-tap decision feedback equalizer (DFE), in the READ direction, to compensate for channel inter-symbol interference (ISI). The receiver front-end contains a supply noise tracking scheme to mitigate reference voltage (VREF) noise. A tri-VCO PLL and an efficient global clock distribution scheme support a wide range of operating frequencies at low power consumption. Finally, the interface also incorporates two overhead links per byte for data-bus encoding (DBE) experiments to mitigate simultaneous switching noise (SSN). Implemented in a 40-nm CMOS process, the × 16 tri-modal interface achieves an energy efficiency of better than 5.0 mW/Gbps per data link at 12.8 Gbps. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/JSSC.2012.2185369 | J. Solid-State Circuits |
Keywords | Field | DocType |
supply noise tracking scheme,cmos process,cmos integrated circuits,bit rate 12.8 gbit/s,gddr5 memory,bit rate 6.4 gbit/s,write direction,low power consumption,multi-modal,read direction,operating frequency,tri-modal single-ended memory interface,driver circuits,voltage-controlled oscillators,global clock distribution scheme,ddr3,receiver front-end,tri-vco pll,simultaneous switching noise,gddr5,vref noise,size 40 nm,low-power electronics,leq,linear equalizer,channel inter-symbol interference,single-ended,dram chips,se signaling,data-bus encoding experiments,phase locked loops,dfe,tri-modal asymmetric memory controller interface,integrated circuit noise,ddr3 memory,reference voltage noise,single-ended signaling,overhead links per byte,compact voltage-mode driver,equalizer,read-only storage,dbe experiments,electrical link,stripline fr4 traces,decision feedback equalisers,bit rate 1.6 gbit/s,1-tap decision feedback equalizer,ssn,reference circuits,energy efficiency,intersymbol interference,memory interface,isi,energy efficient,multi modal,single ended signaling,front end,transistors,impedance,low power electronics,single ended,noise,calibration | Phase-locked loop,Intersymbol interference,Computer science,Voltage reference,CMOS,Electronic engineering,S-LINK,Memory controller,Low-power electronics,Encoding (memory) | Journal |
Volume | Issue | ISSN |
47 | 4 | 0018-9200 |
Citations | PageRank | References |
16 | 2.59 | 8 |
Authors | ||
32 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amir Amirkhany | 1 | 63 | 12.75 |
| Jason Wei | 2 | 18 | 3.30 |
| Navin K. Mishra | 3 | 20 | 3.63 |
| Jie Shen | 4 | 20 | 3.36 |
| Wendemagegnehu T. Beyene | 5 | 37 | 7.29 |
| Catherine Chen | 6 | 18 | 4.66 |
| T. J. Chin | 7 | 20 | 3.36 |
| Deborah Dressler | 8 | 18 | 2.97 |
| Charlie Huang | 9 | 30 | 5.73 |
| Vijay P. Gadde | 10 | 20 | 3.33 |
| Mohammad Hekmat | 11 | 24 | 5.17 |
| Kambiz Kaviani | 12 | 48 | 8.77 |
| Hai Lan | 13 | 47 | 6.49 |
| Phuong Le | 14 | 32 | 6.73 |
| Mahabaleshwara | 15 | 19 | 3.45 |
| Chris J. Madden | 16 | 70 | 9.71 |
| Sanku Mukherjee | 17 | 19 | 3.98 |
| Leneesh Raghavan | 18 | 22 | 3.88 |
| Keisuke Saito | 19 | 21 | 4.96 |
| Dave Secker | 20 | 19 | 3.58 |
| Arul Sendhil | 21 | 19 | 4.31 |
| Ralf Schmitt | 22 | 18 | 2.97 |
| H. Md. Shuaeb Fazeel | 23 | 24 | 3.79 |
| Gundlapalli Shanmukha Srinivas | 24 | 18 | 2.97 |
| Ting Wu | 25 | 20 | 3.36 |
| Chanh Tran | 26 | 18 | 3.30 |
| Arun Vaidyanath | 27 | 18 | 2.97 |
| Kapil Vyas | 28 | 19 | 3.79 |
| Ling Yang | 29 | 16 | 2.59 |
| Manish Jain | 30 | 16 | 2.59 |
| Kun-Yung Ken Chang | 31 | 22 | 3.64 |
| Xingchao Yuan | 32 | 18 | 2.97 |