Name
Abstract | ||
|---|---|---|
An FPGA-based prototype of a custom high-performance network hardware has been implemented, integrating both a switch and a network interface in one FPGA. The network interfaces to the host processor over HyperTransport. About 85% of the slices of a Virtex IV FX100 FPGA are occupied and 10 individual clock domains are used. Six of the MGT-blocks of the device implement high-speed links to other nodes. Together with the integrated switch it is thus possible to build topologies with a node degree of up to 6, i.e. a 3D-torus or a 6D Hypercube. The target clock rate is 156 MHz with the links running at 6.24 Gbit/s and 200 MHz for the HyperTransport Core. This goal was reached with a 32-bit wide data path in the network-switch and link blocks. The integrated switch reaches an aggregate bandwidth of more than 45 Gbit/s. The resulting interconnection network features a very low latency – between nodes and including switching - close to 1 µs. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ReConFig.2009.23 | ReConFig |
Keywords | Field | DocType |
virtex iv fx100 fpga,hypertransport core,integrated switch,fpga-based custom high performance,interconnection network,32-bit wide data path,individual clock domain,fpga-based prototype,target clock rate,custom high-performance network hardware,network interface,switching,optimization,switches,network topology,field programmable gate arrays,integrated circuit design,network,synchronization,circuit topology,crossbar,interconnect,low latency,hypertransport | Computer science,Parallel computing,Networking hardware,Network topology,Virtex,Interconnection,HyperTransport,Crossbar switch,Clock rate,Embedded system,Network interface | Conference |
ISBN | Citations | PageRank |
978-0-7695-3917-1 | 0 | 0.34 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mondrian Nüssle | 1 | 26 | 3.59 |
| Benjamin Geib | 2 | 18 | 1.92 |
| Holger Fröning | 3 | 115 | 24.31 |
| Ulrich Brüning | 4 | 76 | 11.64 |