Name
Title | ||
|---|---|---|
Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology |
Abstract | ||
|---|---|---|
As process technology continues to scale into the nanometer regime, the interplay between dummy fill metal placement and interconnect thickness variation due to chemical mechanical polishing (CMP) has become increasingly important for performance, reliability, and yield. This paper provides the first simultaneous investigation of both the interconnect capacitance increases and the CMP-induced thickness variations associated with rule-based and model-based fill generation methods. The results indicate that dummy fill can have a significant impact on both parasitic capacitance and interconnect planarization for large-scale designs implemented in 65 nm technology. We also demonstrate that model-based methods can simultaneously provide smaller incremental capacitance increases and better interconnect planarization compared to rule-based techniques. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1366110.1366148 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
dummy fill,smaller incremental capacitance increase,cmp-induced thickness variation,parasitic capacitance,capacitance increase,dummy fill metal placement,nm technology,nano-scale process technology,process technology,model-based fill generation method,model-based method,chemical mechanical polishing,design for manufacture,design for manufacturability,rule based | Nanoscopic scale,Capacitance,Parasitic capacitance,Computer science,Electronic engineering,Nanometre,Interconnection,Design for manufacturability,Chemical-mechanical planarization | Conference |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arthur Nieuwoudt | 1 | 207 | 20.59 |
| Jamil Kawa | 2 | 108 | 12.33 |
| Yehia Massoud | 3 | 772 | 113.05 |