Name
Abstract | ||
|---|---|---|
In VLSI layout of interconnection networks, routing two-point nets in some restricted area is one of the central operations. It aims usually to minimize the layout area. Here, we consider connecting (with knock-knees) sets of N inputs and N outputs on the opposite sides of a rectangular channel, where the output order is a given permutation of the order of corresponding inputs. Such channels are used in many types of VLSI layouts, among them interconnection networks. Here we complete the algorithm of Muthukrishnan et al. and correct its analysis, and adjust the algorithm of Pinter for the same problem conditions. |
Year | Venue | Keywords |
|---|---|---|
2006 | PDPTA | vlsi layout,channel routing,area optimization. |
Field | DocType | Citations |
Computer science,Parallel computing,Permutation,Communication channel,Interconnection,Very-large-scale integration,Vlsi layout | Conference | 0 |
PageRank | References | Authors |
0.34 | 4 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maria Artishchev-Zapolotsky | 1 | 0 | 1.35 |