Paper Info
Title
A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid
Abstract
A class-D amplifier with pulse code modulated (PCM) digital input is developed for a low-power digital hearing aid. A 16-bit 40-kbps PCM digital input is noise-shaped by a third-order digital sigma-delta modulator (SDM) which provides 1.5-bit digital output. The 1.5-bit digital output of the digital SDM is converted to a three-level analog signal by a simple digital-to-analog converter (DAC) and then applied to an analog SDM. The analog SDM provides pulse density modulated (PDM) signal to drive a power switch. The PDM output is fed back to the input of the analog SDM in order to suppress the noise of the power switch. While the integrators of the analog SDM are implemented with switched-capacitor (SC) circuits for a well-defined frequency response of the modulator loop filter, the feedback path from the power switch output is realized with a continuous-time (CT) integrator for effective noise suppression. The class-D amplifier with PCM digital input has been implemented in a standard 0.13-μm CMOS process. With 160-Ω load of speaker, the maximum output power delivered to the load is 1.14-mW while the efficiency of the power switch is 97-%. The signalmathchar"702D tomathchar"702D noise+distortion ratio (SNDR) and dynamic range (DR) of the class-D amplifier are measured to be 80.6-dB and 87-dB, respectively. The class-D amplifier consumes 0.38-mW from a 1.2-V power supply including the driving power of the power switch.
Year
DOI
Venue
2013
10.1109/JSSC.2012.2224731
IEEE Journal of Solid-state Circuits
Keywords
DocType
Volume
digital hearing aid,resistance 160 ohm,prosthetic power supplies,noise suppression,switches,pdm signal,low-power digital hearing aid,cmos integrated circuits,analog sdm,sigma-delta modulator,sigma-delta modulation,class-d amplifier,power switching,feedback path,dynamic range,pulse code modulated digital input,pulse density modulated signal,pulse code modulation,sndr,voltage 1.2 v,frequency response,modulator loop filter,standard cmos process,driving power,three-level analog signal,power 0.38 mw,switched-capacitor circuits,space division multiplexing,pcm digital input,third-order digital sigma-delta modulator,power switch,feedback,continuous-time integrator,h-bridge,power supply,signal-to-noise ratio (snr),hearing aids,ct integrator,dac,storage capacity 16 bit,interference suppression,sc circuits,maximum output power,storage capacity 1.5 bit,bit rate 40 kbit/s,size 0.13 mum,cmos,third-order digital sdm,digital-to-analog converter,digital-analogue conversion,signal-to-noise-distortion ratio,power 1.14 mw
Journal
48
Issue
ISSN
Citations 
2
0018-9200
8
PageRank 
References 
Authors
0.54
10
4
Name
Order
Citations
PageRank
Jinho Noh1171.68
Dongjun Lee285584.67
Jun-Gi Jo3192.37
Changsik Yoo411634.39