Name
Abstract | ||
|---|---|---|
Two orthogonal hardware techniques, table-based addressprediction and early address calculation, for reducingthe latency of load instructions have been recentlyproposed. The key idea behind both of thesetechniques is to speculatively perform loads early inthe processor pipeline using predicted values for theloads" addresses. These techniques have required eithera large hardware table or complex register bypasslogic to be implemented in order to accurately predictthe important loads in... |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/MICRO.1998.742776 | MICRO |
Keywords | Field | DocType |
compiler-directed early load-address generation,computer architecture | Instruction scheduling,Cache,Computer science,Latency (engineering),Profiling (computer programming),Parallel computing,Compiler correctness,Real-time computing,Compiler,Heuristics,Speedup | Conference |
ISBN | Citations | PageRank |
1-58113-016-3 | 9 | 0.59 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ben-Chung Cheng | 1 | 151 | 12.31 |
| Daniel A. Connors | 2 | 407 | 33.81 |
| Wen-mei W. Hwu | 3 | 4322 | 511.62 |