Name
Abstract | ||
|---|---|---|
Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/988952.989008 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
monotonic logic,static power,logic gate,logic circuit technique,static power reduction,logic block,logic stage,circuit optimization,wide range,logic circuit design strategy,existing circuit technique,high leakage cmos technology,multilevel model,leakage current,circuit design | Logic gate,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Electronic engineering,Real-time computing,Resistor–transistor logic,Logic family,Register-transfer level,Asynchronous circuit | Conference |
ISBN | Citations | PageRank |
1-58113-853-9 | 3 | 0.53 |
References | Authors | |
17 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Phillip Chin | 1 | 6 | 0.98 |
| Charles A. Zukowski | 2 | 134 | 29.94 |
| George Gristede | 3 | 27 | 4.76 |
| Stephen Kosonocky | 4 | 75 | 11.71 |